1. Field of the Invention
The present invention relates to a complementation device employed in an operator part of a digital information processing system, and more particularly to a 2's complementer having a simple circuit arrangement and yet obtaining a high complementation rate.
2. Description of the Prior Art
Generally, a digital information processing system includes an operator part for performing four basic arithmetic operations, i.e., addition, substraction, multiplication, and division, according to the rules of the addition. For the substraction and division operation, the operator part derives complement of a subtrahend to be added to a minuend and complement of a divisor to be added to a dividend.
As such complements, there are 1's complements and 2's complements. The 2's complements are mainly used because they can simplify the process of the substraction and division, as compared to the 1's complements. Such 2's complements are derived by taking the 1's complements of binary data by bits and then adding "1" to each of the 1's complements. Otherwise, 2's complements may be derived by inverting higher-order bits of binary data than the first one of bits having the value of logic-1 on an order-by-order basis starting with the least-significant bit (LSB) and ending with the most-significant bit (MSB). The first method have been hardly used because of its troublesome operation involving the addition of "1" after deriving of 1's complements. The second method have been mainly used because it enables a simple circuit arrangement to be constructed and a rapid operation rate to be obtained.
However, existing 2's complementers utilizing the second method encounter problems that the circuit arrangement becomes more complex and the complement driving rate is gradually reduced as the number of bits of the data to be complemented is increased. This is because the second method is performed on an order-by-order basis starting with the LSB and ending with the MSB. These problems encountered in the conventional 2's complementers utilizing the second method will be described in detail, in conjunction with FIG. 1.
FIG. 1 is a circuit diagram of a conventional 2' complementer. As shown in FIG. 1, the 2' complementer includes four exclusive OR gates 10, 12, 14 and 16 for receiving binary data of 4 bits respectively applied to four input lines 11, 13, 15 and 17, and four AND gates 18, 20, 22 and 24 for receiving an enable signal EN from a control line 19 in common. The first AND gate 18 performs the AND operation between the enable signal EN and a carry signal received from a fifth input line 21. For a complementation, the enable signal EN has the high logic value. The first exclusive OR gate 10 outputs the value of logic-0 to the first output line 23 when LSB data from the first input line 11 has the same logic value as the output from the first AND gate 18. On the contrary, when LSB data from the first input line 11 has a different logic value from the output from the first AND gate 18, the first exclusive OR gate 10 outputs the value of logic-1 to the first output line 23. As a result, the first exclusive OR gate 10 inverts the LSB data when the carry signal has the value of logic-1. On the contrary, when the carry signal has the value of logic-0, the first exclusive OR gate 10 sends the LSB signal, as it is, to the first output line 23.
This 2's complementer further includes a first OR gate 26 for performing the OR operation between the LSB data from the first input line 11 and the carry signal from the fifth input line 21, a second OR gate 28 for performing the OR operation between the second LSB data from the second input line 13 and the output signal from the first OR gate 26, and a third OR gate 30 for performing the OR operation between the second MSB data from the third input line 15 and the output signal from the second OR gate 28.
The second AND gate 20 performs the AND operation between the enable signal EN and the output signal from the first OR gate 26 and supplies the result of the AND operation to the second exclusive OR gate 12. The second exclusive OR gate 12 then compares the output signal from the second AND gate 20 with the second LSB data and supplies the result of the comparison to the second output line 25. When the output signal from the first OR gate 26 has the value of logic-1, the data sent to the second output line 25 has the same logic value as the inverted second LSB data. On the contrary, the data on the second output line 25 has the same logic value as the second LSB data when the output signal from the first OR gate 26 has the value of logic-0.
The third AND gate 22 performs the AND operation between the enable signal EN and the output signal from the second OR gate 28 and supplies the result of the AND operation to the third exclusive OR gate 14. In similar, the fourth AND gate 24 performs the AND operation between the enable signal EN and the output signal from the third OR gate 30 and supplies the result of the AND operation to the fourth exclusive OR gate 16. In similar to the second exclusive OR gate 12, the third exclusive OR gate 14 applies to the third output line 27 the inverted second MSB data or the second MSB data, based on the logic value of the output signal from the second OR gate 28. In similar to the third exclusive OR gate 14, the fourth exclusive OR gate 16 applies to the third output line 27 the inverted MSB data or the MSB data, based on the logic value of the output signal from the third OR gate 30.
In actual, where the 2's complementer receives data having logic values of 0, 0, 1 and 0 via the first to fourth input lines 11, 13, 15 and 17, it generates 2's-complement data having logic values of 1, 1, 1 and 0.
However, since the conventional 2's complementer operates binary data from LSB data to MSB data in a sequential manner, the complementation rate is lowered as the number of bits of the data to be complemented is increased. Furthermore, the conventional 2's complementer encounters the problem that the circuit thereof becomes more complex as the number of bits of the data to be complemented is increased.